To avoid electro-magnetic interference (EMI) generated by high frequency signals, frequency jittering is a method that is often used in high frequency electronic products. Conventionally, frequency jittering is achieved by means of a digital counter; following the counts generated by the digital counter, the frequency shifts within a narrow range. A typical frequency jittering control circuit employing a digital counter may be found in U.S. Pat. No. 6,229,366, which in a simplified form is as shown in FIG. 1: a counter 14 counts the output signal pulses from an oscillator 12, and a digital-to-analog circuit (DAC) 16 generates different signals according to the count of the counter 14. The output of the DAC 16 is fed back to the oscillator 12 to shift its output frequency in a narrow range, which is referred to as “jittered frequency”.
Referring to FIG. 2, in a power management chip, the output of the oscillator 12 is usually supplied to a pulse width modulation (PWM) circuit 18; the PWM circuit 18 drives a power stage circuit 20 to convert an input voltage Vin to an output voltage Vout, which is supplied to a load. The power stage circuit 20 for example may be a switching regulator, a fly-back regulator, or any other voltage regulator. Usually it is only in a heavy-load condition that a power switch (not shown) inside the power stage circuit 20 has to switch in high frequency, which requires frequency jittering. In a light-load or no-load condition, frequency jittering is not required, and undesired, because it increases the ripple.
The U.S. Pat. No. 6,229,366 has a drawback that it does not deal with the connection between frequency jittering and load conditions.